The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Jun. 29, 2016
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Chih Chun Tai, Shanghai, CN;

Lei Fang, Shanghai, CN;

Dae Sub Jung, Shanghai, CN;

Gangning Wang, Shanghai, CN;

Guangli Yang, Shanghai, CN;

Jiao Wang, Shanghai, CN;

Hong Sun, Shanghai, CN;

Yunpeng Peng, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823892 (2013.01); H01L 21/823814 (2013.01); H01L 27/0928 (2013.01); H01L 29/0847 (2013.01); H01L 29/36 (2013.01); H01L 29/66598 (2013.01); H01L 29/7833 (2013.01);
Abstract

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.


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