The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Jul. 15, 2013
Applicant:

Gigadevice Semiconductor (Beijing) Inc., Beijing, CN;

Inventors:

Qingming Shu, Beijing, CN;

Hong Hu, Beijing, CN;

Sai Zhang, Beijing, CN;

Jianjun Zhang, Beijing, CN;

Jiang Liu, Beijing, CN;

Ronghua Pan, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G06F 3/06 (2006.01); H01L 25/00 (2006.01); G06F 13/42 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0626 (2013.01); G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 13/4291 (2013.01); H01L 25/50 (2013.01); H01L 24/06 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1438 (2013.01);
Abstract

An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.


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