The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Aug. 12, 2016
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Haiyang Zhang, Shanghai, CN;

Chenglong Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/205 (2013.01); H01L 21/02543 (2013.01); H01L 21/30621 (2013.01); H01L 29/66522 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

The disclosed subject matter provides a Fin-FET with a thinned-down InP layer and thinning-down method thereof. In a Fin-FET, the fin structure is made of InGaAs and an InP layer is formed to cover the fin structure. The InP layer is obtained from an initial InP layer formed on the fin structure through a thinning down process including converting a surface portion of the InP layer into a Phosphorus-rich layer and removing the Phosphorus-rich layer. The thickness of the ultimately-formed InP layer is less than or equal to 1 nm. According to the disclosed method, the InP layer in the Fin-FET may be easily thinned down, and during the thinning-down process, contamination may be avoided.


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