The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2017
Filed:
Aug. 17, 2016
Seulye Kim, Hwasung-si, KR;
Ji-hoon Choi, Seongnam-si, KR;
Dongkyum Kim, Suwon-si, KR;
Jung Ho Kim, Seongnam-si, KR;
Jintae Noh, Yongin-si, KR;
Eun-young Lee, Suwon-si, KR;
Seulye Kim, Hwasung-si, KR;
Ji-Hoon Choi, Seongnam-si, KR;
Dongkyum Kim, Suwon-si, KR;
Jung Ho Kim, Seongnam-si, KR;
Jintae Noh, Yongin-si, KR;
Eun-Young Lee, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.