Electrostatic discharge (esd) protection transistor devices and integrated circuits with electrostatic discharge protection transistor devices

Abstract

An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.