The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Jul. 09, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventor:

Leilei Zhang, Sunnyvale, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/81 (2013.01); H01L 23/50 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit die electrically coupled to the electrically conductive grid at one or more locations. In this embodiment, the electrically conductive grid includes a plurality of electrically conductive portions, wherein each portion is electrically coupled to at least one other portion, and a plurality of void regions that are electrically non-contiguous and substantially free of electrically conductive material. One advantage of the integrated circuit package is that a packaging substrate that is reduced in thickness, and therefore rigidity, can still maintain planarity during operation. The electrically conductive grid formed on a dielectric layer in the packaging substrate can replace a power plane or a ground plane in the packaging substrate, thereby reducing stressed produced as a result of thermal expansion mismatch between materials in the packaging substrate.


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