The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Apr. 25, 2016
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

David Kung, Foster City, CA (US);

David Michael Hugh Matthews, Los Gatos, CA (US);

Balu Balakrishnan, Saratoga, CA (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H05K 7/18 (2006.01); H04B 5/00 (2006.01); H04B 1/00 (2006.01); H01L 23/552 (2006.01); H04B 15/00 (2006.01); H05K 7/14 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/3114 (2013.01); H01L 23/48 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 23/5227 (2013.01); H01L 27/0248 (2013.01); H01L 28/10 (2013.01); H04B 15/005 (2013.01); H05K 7/14 (2013.01); H01L 24/48 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2924/00014 (2013.01);
Abstract

An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes first and second conductive loops. A first voltage is induced between first and second ends of the first conductive loop in response to an external magnetic field that passes through the integrated circuit package. A second voltage is induced between third and fourth ends of the second conductive loop of the lead frame in response to the external magnetic field that passes through the integrated circuit package. The first conductive loop is coupled to the second conductive loop such that the first voltage between the first and second ends combined with the second voltage between the third and fourth ends substantially cancel.


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