The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Nov. 06, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Woon-Seong Kwon, Cupertino, CA (US);

Suresh Ramalingam, Fremont, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/67 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/67126 (2013.01); H01L 23/3142 (2013.01);
Abstract

Techniques for providing a unified underfill and encapsulation for integrated circuit die assemblies. These techniques include a molding technique that includes dipping a die assembly including a substrate and one or more dies into a chamber having molding material, sealing the chamber, and lowering pressure in the chamber to coax the molding material into space between the die(s) and substrate. The use of this molding technique, as contrasted with a capillary underfill technique in which underfill material is laid down adjacent dies and fills space under the die via capillary action, provides several benefits. One benefit is that the molding material can include a higher silica particle filler content (% by weight) than the material for the capillary underfill technique, which improves CTE. Another benefit is that various design constraints related to, for example, warpage and partial underfill are eliminated or improved.


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Kwon, Woon-Seong. (2017). Techniques for molded underfill for integrated circuit dies (U.S. Patent No. 9831104). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9831104

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