The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
May. 26, 2015
Applicant:
Arteris, Inc, Campbell, CA (US);
Inventors:
Xavier van Ruymbeke, Issy les Moulineaux, FR;
Monica Tang, San Jose, CA (US);
Jonah Probell, Alviso, CA (US);
Aliaksei Chapyzhenka, San Jose, CA (US);
Assignee:
ARTERIS, Inc., Campbell, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H04L 12/54 (2013.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
H04L 12/56 (2013.01); G06F 17/5045 (2013.01); H04L 12/54 (2013.01); H04L 49/109 (2013.01);
Abstract
A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.