The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Dec. 20, 2013
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Kazuma Mima, Osaka, JP;

Seiichi Nakatani, Osaka, JP;

Yoshihisa Yamashita, Kyoto, JP;

Koji Kawakita, Nara, JP;

Susumu Sawada, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 33/00 (2010.01); H01L 23/02 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); C25D 7/12 (2006.01); C25D 11/32 (2006.01); H01L 33/62 (2010.01); H01L 33/64 (2010.01); H01L 21/48 (2006.01); H01L 33/52 (2010.01); H01L 21/768 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 21/4846 (2013.01); H01L 33/52 (2013.01); H01L 33/64 (2013.01); H01L 21/56 (2013.01); H01L 21/76873 (2013.01); H01L 21/76874 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 23/481 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03825 (2013.01); H01L 2224/2746 (2013.01); H01L 2224/27462 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/19105 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01); H01L 2933/0075 (2013.01);
Abstract

A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.


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