The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Mar. 12, 2015
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Kyohei Fukuda, Matsumoto, JP;

Tatsuo Nishizawa, Matsumoto, JP;

Yuhei Nishida, Matsumoto, JP;

Eiji Mochizuki, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/12 (2006.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 23/24 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); H01L 23/12 (2013.01); H01L 23/24 (2013.01); H01L 23/49531 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 23/522 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.


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