Memory systems with multiple modules supporting simultaneous access responsive to common memory commands

Abstract

Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.