The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Feb. 19, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Michael A. Sadd, Austin, TX (US);

Anirban Roy, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G06F 3/06 (2006.01); G11C 14/00 (2006.01); G11C 11/00 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0647 (2013.01); G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G11C 11/005 (2013.01); G11C 14/009 (2013.01); G11C 7/12 (2013.01);
Abstract

The present disclosure provides embodiments for methods and memory devices. One embodiment of a memory device includes a first volatile memory cell having a first volatile access transistor with a current electrode coupled with a first volatile bit line; a first non-volatile memory cell having a first non-volatile access transistor with a current electrode coupled with a first non-volatile bit line; and a transfer circuit coupled between the first volatile bit line and the first non-volatile bit line. The transfer circuit is configured to: couple data latched from the first volatile bit line with the first non-volatile bit line during a store operation, and couple the first volatile bit line with the first non-volatile bit line during a restore operation.


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