The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
Jan. 07, 2016
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Meir Ovadia, Rosh Ha-ayin, IL;
Swaminathan Venkateasan, Irvine, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/3177 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G06F 17/5009 (2013.01); G06F 17/5022 (2013.01); G06F 17/5027 (2013.01); G06F 17/5036 (2013.01); G01R 31/2851 (2013.01);
Abstract
A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.