The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Dec. 18, 2014
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Ron Rotstein, Tel Aviv, IL;

Gil Zukerman, Hod-HaSharon, IL;

Zeev Gil-Ad, Qiriat-Onoi, IL;

Assignee:

INTEL IP CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/58 (2006.01); H04L 12/26 (2006.01); H04L 12/40 (2006.01); H04L 29/06 (2006.01); H04L 12/813 (2013.01);
U.S. Cl.
CPC ...
H04L 43/04 (2013.01); H04L 12/40013 (2013.01); H04L 69/18 (2013.01); H04L 47/20 (2013.01);
Abstract

A single high-speed bus accommodates both low-rate and high-rate bi-directional signal traffic by interleaving the traffic at the two rates sequentially so that all the data in the bus at any given time is either high-rate or low-rate. The interleaving is executed by a statistical aggregator according to a policy tailored to the traffic expected in the particular bus. The policy may be static and predetermined, or it may be dynamic and adaptive. Adaptive policies are continually updated with predictions of future traffic based on the statistics of past and/or present traffic. The technique may be implemented in both on-chip and system-level bus interfaces.


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