The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Apr. 01, 2016
Applicant:

Fujitsu Semiconductor Limited, Yokohama-shi, Kanagawa, JP;

Inventors:

Kazutaka Yoshizawa, Yokohama, JP;

Taiji Ema, Yokohama, JP;

Takuya Moriki, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 23/544 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/78 (2013.01); H01L 22/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/544 (2013.01); H01L 23/564 (2013.01); H01L 24/05 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/5448 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/05093 (2013.01); H01L 2224/05553 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.


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