The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Oct. 14, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Richard Stephen Graf, Gray, ME (US);

David Justin West, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 22/10 (2013.01); H01L 21/565 (2013.01); H01L 23/49811 (2013.01); H01L 24/83 (2013.01); H01L 25/10 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 22/14 (2013.01); H01L 23/3128 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.


Find Patent Forward Citations

Loading…