The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

May. 01, 2017
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Sylvain Joblot, Bizonnes, FR;

Pierre Bar, Grenoble, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 21/762 (2006.01); H01L 23/66 (2006.01); H01P 11/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/4846 (2013.01); H01L 21/76224 (2013.01); H01L 23/66 (2013.01); H01P 11/003 (2013.01); G02B 6/12 (2013.01);
Abstract

An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.


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