The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Jan. 27, 2016
Mentor Graphics Corporation, Wilsonville, OR (US);
Alan Sherman, Silver Spring, MD (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
This application discloses tools to build a topology library including one or more topologies, each of which includes a description of multiple transistors, their parameters, and associated connectivity, and also includes rules or criteria to be utilized in downstream design flow processes. The tools can analyze a circuit design describing an electronic device to recognize a subset of transistors in the electronic device has a pre-defined circuit topology, and identify layout rules or simulation criteria for the transistors in the recognized circuit topology. The tools can utilize the layout rules to automatically generate a portion of a physical design layout corresponding to the recognized topology in the circuit design. The tools also can compare results from a simulation of the circuit design that correspond to the transistors in the recognized circuit topology to the simulation criteria to determine whether the transistors in the recognized circuit topology meet design specifications.