The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Mar. 20, 2015
Calypto Design Systems, Inc., San Jose, CA (US);
Pankaj P. Chauhan, San Ramon, CA (US);
Sameer Kapoor, Milpitas, CA (US);
Saurabh Jain, Noida, IN;
Kunal Bindal, Munich, DE;
Bryan D. Bowyer, Wilsonville, OR (US);
Andres R. Takach, Wilsonville, OR (US);
Peter P. Gutberlet, Wilsonville, OR (US);
Gagandeep Singh, Noida, IN;
Maheshinder Goyal, Noida, IN;
Calypto Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level ('RTL') circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.