The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Sep. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mauricio Breternitz, Jr., Austin, TX (US);

Youfeng Wu, Palo Alto, CA (US);

Cheng Wang, San Ramon, CA (US);

Edson Borin, San Jose, CA (US);

Shiliang Hu, Los Altos, CA (US);

Craig B. Zilles, Champaign, IL (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 8/443 (2013.01); G06F 8/52 (2013.01); G06F 9/3004 (2013.01); G06F 9/30072 (2013.01); G06F 9/30087 (2013.01); G06F 9/30116 (2013.01); G06F 9/3842 (2013.01); G06F 9/3857 (2013.01); G06F 9/466 (2013.01); G06F 11/3672 (2013.01); G06F 11/3688 (2013.01);
Abstract

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.


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