The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Dec. 28, 2012
Intel Corporation, Santa Clara, CA (US);
Thanunathan Rangarajan, Bangalore, IN;
Shreesh Chhabbi, Bangalore, IN;
Arvind A. Kumar, Beaverton, OR (US);
Venkatraman Iyer, Austin, TX (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.