The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Dec. 01, 2015
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventors:

Hugo Burke, Llantrisant, GB;

Ling Ma, Redondo Beach, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/76877 (2013.01); H01L 29/495 (2013.01); H01L 29/4991 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.


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