The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Feb. 13, 2015
Applicants:

Ju-youn Kim, Suwon-si, KR;

Ji-hwan an, Seoul, KR;

Kwang-yul Lee, Suwon-si, KR;

Tae-won Ha, Seongnam-si, KR;

Jeong-nam Han, Seoul, KR;

Inventors:

Ju-Youn Kim, Suwon-si, KR;

Ji-Hwan An, Seoul, KR;

Kwang-Yul Lee, Suwon-si, KR;

Tae-Won Ha, Seongnam-si, KR;

Jeong-Nam Han, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/28185 (2013.01); H01L 21/823431 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/28088 (2013.01); H01L 21/31138 (2013.01); H01L 21/32139 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.


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