The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Jan. 18, 2017
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Hsueh-Wei Chen, Hsinchu, TW;

Wei-Ren Chen, Pingtung County, TW;

Wein-Town Sun, Taoyuan, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0408 (2013.01); G11C 16/14 (2013.01); H01L 27/11519 (2013.01);
Abstract

A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.


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