The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Jun. 26, 2013
Applicant:

Novellus Systems, Inc., Fremont, CA (US);

Inventors:

Daniel Mark Dinneen, Tigard, OR (US);

James E. Duncan, Beaverton, OR (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G01N 21/00 (2006.01); B23K 26/00 (2014.01); G01R 31/26 (2014.01); H01L 21/44 (2006.01); H04N 9/47 (2006.01); C25D 17/00 (2006.01); H01L 21/67 (2006.01); C25D 21/10 (2006.01); C25D 21/12 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
C25D 17/001 (2013.01); C25D 21/10 (2013.01); C25D 21/12 (2013.01); H01L 21/67253 (2013.01); H01L 21/0209 (2013.01); H01L 21/02087 (2013.01); H01L 21/76877 (2013.01);
Abstract

Disclosed herein are electroplating systems for forming a layer of metal on a wafer which include an electroplating module and a wafer edge imaging system. The electroplating module may include a cell for containing an anode and an electroplating solution during electroplating, and a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating. The wafer edge imaging system may include a wafer holder for holding and rotating the wafer through different azimuthal orientations, a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while it is held and rotated (the process edge corresponding to the outer edge of the layer of metal formed on the wafer), and image analysis logic for determining an edge exclusion distance, wherein the edge exclusion distance is a distance between the wafer's edge and the process edge.


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