The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Oct. 26, 2011
Applicants:

Marie Denison, Plano, TX (US);

Philip L. Hower, Concord, MA (US);

Sameer Pendharkar, Allen, TX (US);

Inventors:

Marie Denison, Plano, TX (US);

Philip L. Hower, Concord, MA (US);

Sameer Pendharkar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 29/861 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7824 (2013.01); H01L 27/1203 (2013.01); H01L 29/1087 (2013.01); H01L 29/7818 (2013.01); H01L 29/7835 (2013.01); H01L 29/861 (2013.01); H01L 27/0629 (2013.01);
Abstract

An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).


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