The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jun. 16, 2016
Applicant:

Nexperia B.v., Eindhoven, NL;

Inventors:

Hans-Juergen Funke, Luebeck, DE;

Tobias Sprogies, Hamburg, DE;

Rolf Brenner, Hamburg, DE;

Rüdiger Weber, Pinneberg, DE;

Wolfgang Schnitt, Hamburg, DE;

Frank Burmeister, Hamburg, DE;

Assignee:

Nexperia B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01);
Abstract

A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.


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