The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Oct. 17, 2011
Applicants:

James E. Jaussi, Hillsboro, OR (US);

Stephen R. Mooney, Mapleton, UT (US);

Howard L. Heck, Hillsboro, OR (US);

Bryan K. Casper, Portland, OR (US);

Frank T. Hady, Portland, OR (US);

Inventors:

James E. Jaussi, Hillsboro, OR (US);

Stephen R. Mooney, Mapleton, UT (US);

Howard L. Heck, Hillsboro, OR (US);

Bryan K. Casper, Portland, OR (US);

Frank T. Hady, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/266 (2013.01); G06F 1/3203 (2013.01);
Abstract

Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.


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