The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Dec. 19, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andreas Jörn Leistner, Grasbrunn, DE;

Georgios Palaskas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/08 (2006.01); G06F 1/025 (2006.01); H04B 15/06 (2006.01); H04J 11/00 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04L 27/12 (2006.01);
U.S. Cl.
CPC ...
H04L 25/08 (2013.01); G06F 1/025 (2013.01); H04B 15/06 (2013.01); H04J 11/0063 (2013.01); H04L 7/0091 (2013.01); H04L 7/0331 (2013.01); H04L 27/122 (2013.01); H04J 2011/0096 (2013.01);
Abstract

Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.


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