logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9799571 B1

PDFFull Text
Date of Patent:
Oct. 24, 2017

Filed:

Jul. 15, 2015

Methods for producing integrated circuits with interposers and integrated circuits produced from such methods

Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shunqiang Gong, Singapore, SG;

Juan Boon Tan, Singapore, SG;

Assignee:

GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;

Attorney:

Lorenz & Kopf, LLP

Primary Examiner:

Matthew Landau

Assistant Examiner:

Grant Withers

Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); H01L 21/481 (2013.01); H01L 22/32 (2013.01); H01L 22/34 (2013.01); H01L 23/498 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes producing an interposer with an insulation plate and a plurality of through vias passing through the insulation plate. The interposer has a prime area and an in prime area. A prime area test circuit is formed in the prime area, where the prime area test circuit includes a portion of the plurality of through vias that are electrically connected in series.

Find Patent Forward Citations

Gong, Shunqiang. (2017). Methods for producing integrated circuits with interposers and integrated circuits produced from such methods (U.S. Patent No. 9799571). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9799571

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…