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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793906 B1

PDFFull Text
Date of Patent:
Oct. 17, 2017

Filed:

Aug. 30, 2016

Range and process compensation for a digital phase locked loop (pll) or frequency locked loop (fll) circuit

Applicant:

Stmicroelectronics International N.v., Amsterdam, NL;

Inventor:

Gagan Midha, Panipat, IN;

Assignee:

STMicroelectronics International N.V., Schiphol, NL;

Attorney:

Gardere Wynne Sewell LLP

Primary Examiner:

Daniel Puentes

Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/10 (2006.01); H03L 7/183 (2006.01); H03L 7/083 (2006.01); H03L 7/091 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/10 (2013.01); H03L 7/083 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01); H03L 7/183 (2013.01);
Abstract

A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.

Find Patent Forward Citations

Midha, Gagan. (2017). Range and process compensation for a digital phase locked loop (pll) or frequency locked loop (fll) circuit (U.S. Patent No. 9793906). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9793906

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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