The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jul. 13, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Kazuto Takao, Tsukuba, JP;

Tatsuo Shimizu, Shinagawa, JP;

Takashi Shinohe, Yokosuka, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/315 (2006.01); H02M 7/537 (2006.01); H03K 17/04 (2006.01); H03K 17/0412 (2006.01); H03K 17/042 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
H02M 7/537 (2013.01); H03K 17/0406 (2013.01); H03K 17/04123 (2013.01); H03K 17/04206 (2013.01); H03K 17/164 (2013.01); H03K 17/166 (2013.01); H03K 17/168 (2013.01); H03K 2217/0036 (2013.01);
Abstract

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.


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