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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793474 B1

PDFFull Text
Date of Patent:
Oct. 17, 2017

Filed:

Feb. 24, 2014

Low temperature p+ polycrystalline silicon material for non-volatile memory device

Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Xin Sun, Albany, CA (US);

Sung Hyun Jo, Sunnyvale, CA (US);

Tanmay Kumar, Pleasanton, CA (US);

Assignee:

CROSSBAR, INC., Santa Clara, CA (US);

Attorney:

Amin, Turocy & Watson, LLP

Primary Examiner:

Long K Tran

Assistant Examiner:

Thai T Vuong

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/20 (2006.01); H01L 21/8239 (2006.01); H01L 45/00 (2006.01); H01L 27/10 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/145 (2013.01); H01L 27/101 (2013.01); H01L 27/2463 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/148 (2013.01); H01L 45/1616 (2013.01); H01L 45/1675 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01);
Abstract

A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

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