The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Dec. 17, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Pan-Kwi Park, Incheon, KR;

Koung-Min Ryu, Hwaseong-si, KR;

Moon-Han Park, Yongin-si, KR;

Hyung-suk Jung, Suwon-si, KR;

Jong-hoon Baek, Ansan-si, KR;

Su-Young Choi, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823481 (2013.01); H01L 21/823878 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/165 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.


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