The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Mar. 21, 2017
Applicant:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Inventor:

Roger S. Tsai, Torrance, CA (US);

Assignee:

Northrop Gumman Systems Corporation, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/15 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/778 (2006.01); H03F 3/193 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/205 (2006.01); H03F 1/32 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/152 (2013.01); H01L 21/823412 (2013.01); H01L 27/0886 (2013.01); H01L 29/0692 (2013.01); H01L 29/205 (2013.01); H01L 29/41758 (2013.01); H01L 29/7783 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); H03F 1/3205 (2013.01); H03F 3/193 (2013.01); H03F 2200/451 (2013.01); H03F 2201/3215 (2013.01);
Abstract

An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.


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