The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jan. 20, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Naoya Yoshimura, Kanazawa Ishikawa, JP;

Hideaki Ninomiya, Nomi Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/739 (2006.01); H01L 21/66 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0619 (2013.01); H01L 22/10 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01);
Abstract

According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate insulating layer, a fourth semiconductor region of the second conductivity type, a first conductive unit and a first insulating layer. The fourth semiconductor region is provided selectively on the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. At least a portion of the first conductive unit is surrounded with the fourth semiconductor region. At least a portion of the first insulating layer is provided between the first conductive unit and the fourth semiconductor region. A thickness of a portion of the first insulating layer is thinner than a film thickness of the gate insulating layer.


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