The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jan. 12, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Meng-Jia Lin, Changhua County, TW;

Yung-Hsiao Lee, Hsinchu County, TW;

Weng-Yi Chen, Hsinchu County, TW;

Shih-Wei Li, Taoyuan, TW;

Chung-Hsien Liu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); B81B 7/008 (2013.01); B81B 2201/0285 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/012 (2013.01); B81C 2201/014 (2013.01); B81C 2201/0132 (2013.01);
Abstract

A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.


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