The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Sep. 21, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Lianjun Liu, Chandler, AZ (US);

Amitava Bose, Tempe, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B81C 1/00 (2006.01); G01L 9/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0027 (2013.01); B81C 1/00246 (2013.01); G01L 9/0052 (2013.01); B81B 2201/0264 (2013.01); B81B 2207/015 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/053 (2013.01);
Abstract

A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.


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