The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Dec. 20, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Miaobin Gao, Saratoga, CA (US);

Christine M. Krause, Santa Cruz, CA (US);

Hiu-Chin Wu, Cupertino, CA (US);

Hengju Cheng, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H04B 3/02 (2006.01); H01L 23/48 (2006.01); H03F 1/34 (2006.01); H03F 3/08 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45475 (2013.01); H01L 23/48 (2013.01); H03F 1/34 (2013.01); H03F 3/087 (2013.01); H03F 3/45183 (2013.01); H04B 3/02 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2924/0002 (2013.01); H03F 2203/45112 (2013.01); H03F 2203/45206 (2013.01); H03F 2203/45288 (2013.01); H03F 2203/45528 (2013.01); H03F 2203/45641 (2013.01); H03F 2203/45646 (2013.01); H03F 2203/45674 (2013.01); H03F 2203/45702 (2013.01); H03F 2203/45726 (2013.01); H03F 2203/45732 (2013.01);
Abstract

Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.


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