The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Dec. 09, 2015
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Bomy Chen, Newark, CA (US);

Sonu Daryanani, Tempe, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 23/552 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 27/11543 (2017.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 27/11524 (2017.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/788 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); G11C 16/0408 (2013.01); G11C 16/06 (2013.01); H01L 21/266 (2013.01); H01L 21/2652 (2013.01); H01L 23/552 (2013.01); H01L 27/11524 (2013.01); H01L 27/11543 (2013.01); H01L 29/0653 (2013.01); H01L 29/0856 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/66674 (2013.01); H01L 29/66681 (2013.01); H01L 29/66825 (2013.01); H01L 29/7801 (2013.01); H01L 29/7883 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.


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