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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9786776 B1

PDFFull Text
Date of Patent:
Oct. 10, 2017

Filed:

Sep. 09, 2016

Vertical semiconductor device and manufacturing method thereof

Applicant:

Richtek Technology Corporation, Chupei, HsinChu, TW;

Inventors:

Tsung-Yi Huang, Hsinchu, TW;

Chien-Wei Chiu, Yunlin, TW;

Assignee:

RICHTEK TECHNOLOGY CORPORATION, Chupei, Hsinchu, TW;

Attorney:

Tung & Associates

Primary Examiner:

Benjamin Sandvik

Assistant Examiner:

Damon Hillman

Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 21/331 (2006.01); H01L 21/329 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 23/48 (2006.01); H01L 29/732 (2006.01); H01L 29/739 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 23/481 (2013.01); H01L 29/0817 (2013.01); H01L 29/1004 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/6631 (2013.01); H01L 29/66212 (2013.01); H01L 29/66318 (2013.01); H01L 29/66333 (2013.01); H01L 29/66462 (2013.01); H01L 29/732 (2013.01); H01L 29/7395 (2013.01); H01L 29/7788 (2013.01); H01L 29/872 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

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