The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2017
Filed:
Mar. 30, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Peter L. D. Chang, Portland, OR (US);
Uygar E. Avci, Portland, OR (US);
David Kencke, Beaverton, OR (US);
Ibrahim Ban, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10802 (2013.01); H01L 27/10844 (2013.01); H01L 29/0649 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/785 (2013.01); H01L 29/7841 (2013.01);
Abstract
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.