The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Sep. 17, 2015
Applicants:

Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd., Qinhuangdao, CN;

Fukui Precision Component (Shenzhen) Co., Ltd., Shenzhen, CN;

Zhen Ding Technology Co., Ltd., Tayuan, Taoyuan, TW;

Inventor:

Wei-Shuo Su, New Taipei, TW;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 41/047 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 41/0475 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01); H01L 23/49894 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01);
Abstract

A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer, a first conductive pattern and a bearing layer located at opposite sides. The bearing layer corresponds to the laminated area. A second dielectric layer and a second conductive pattern are formed on the first conductive pattern. A third dielectric layer and a third conductive pattern are formed on the bearing layer. All of the second and third dielectric layers, and the second and third conductive pattern corresponds to the laminated area. A first solder resist layer is formed on the second conductive layer. The first solder resist layer defines a plurality of openings, a portion of the second conductive pattern is exposed from the openings defining a plurality of first pads.


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