The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Feb. 17, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Scott R. Cyr, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G11C 5/02 (2006.01); H01L 25/00 (2006.01); G11C 5/06 (2006.01); G11C 8/12 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 5/066 (2013.01); G11C 8/12 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06572 (2013.01);
Abstract

Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal.


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