The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Feb. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ivan Herrera Mejia, Folsom, CA (US);

Manuel A. Aguilar Arreola, Folsom, CA (US);

Shrinivas Venkatraman, Folsom, CA (US);

Andrea R. Vavra, El Dorado Hills, CA (US);

Pavel Konev, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01); G06F 9/44 (2006.01); G06F 13/40 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 9/4411 (2013.01); G06F 13/385 (2013.01); G06F 13/4072 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.


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