The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Mar. 27, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Thiam Wah Loh, Singapore, SG;

Per Hammarlund, Hillsboro, OR (US);

Andreas Wasserbauer, Pettenbach, AT;

Swee Chong Peter Kuan, Singapore, SG;

Eckhard Delfs, Nuremberg, DE;

Deepak A. Mathaikutty, Santa Clara, CA (US);

Stephen J. Robinson, Austin, TX (US);

Gautham N. Chinya, Hillsboro, OR (US);

Perry H. Wang, San Jose, CA (US);

Chee Weng Tan, Singapore, SG;

Hong Wang, Santa Clara, CA (US);

Reza Fortas, Villeneuve Loubet, FR;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G11C 29/52 (2006.01); G06F 21/57 (2013.01); G11C 7/10 (2006.01); G06F 21/10 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 12/1491 (2013.01); G06F 21/10 (2013.01); G06F 21/575 (2013.01); G06F 2212/1052 (2013.01); G06F 2221/032 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.


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