The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9785436 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 10, 2017

Filed:

Sep. 28, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Edward T. Grochowski, San Jose, CA (US);

Dennis R. Bradford, Portland, CA (US);

George Z. Chrysos, Portland, OR (US);

Andrew T. Forsyth, Kirkland, WA (US);

Michael D. Upton, Seattle, WA (US);

Lisa K. Wu, New York, NY (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/34 (2006.01); G06F 9/35 (2006.01); G06F 9/345 (2006.01); G06F 9/355 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 9/30018 (2013.01); G06F 9/30043 (2013.01); G06F 9/30145 (2013.01); G06F 9/345 (2013.01); G06F 9/355 (2013.01);
Abstract

An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.


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