The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Aug. 02, 2016
Applicant:

Integrated Silicon Solution, Inc., Milpitas, CA (US);

Inventor:

Kim C. Hardee, Colorado Springs, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 5/24 (2006.01); H03K 19/0175 (2006.01); G11C 29/50 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0005 (2013.01); G11C 29/50008 (2013.01); H03K 5/24 (2013.01); H03K 19/017545 (2013.01); H03K 19/017581 (2013.01); H03K 19/018557 (2013.01); H03K 19/018585 (2013.01); H03K 2217/94031 (2013.01);
Abstract

Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.


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