The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Dec. 04, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Fu Hsu, Tainan, TW;

Chun-Yuan Wu, Yun-Lin County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.


Find Patent Forward Citations

Loading…